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[SourceCode] signed four bit multiplier

Description: a multiplier for four bit binary number
Platform: | Size: 319 | Author: milk19182000@yahoo.com.tw | Hits:

[VHDL-FPGA-Verilog] BoothMultiplier

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
Platform: | Size: 2048 | Author: 罗兰 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[Other] booth

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check --- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check
Platform: | Size: 1024 | Author: leanne | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] bmul32

Description: 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用-Use VHDL to write a 32-bit parallel multiplier source code, has already been verified, you can directly use
Platform: | Size: 1024 | Author: zh | Hits:

[VHDL-FPGA-Verilog] bmul32_test

Description: 32位并行乘法器的测试文件，已经经过验证，可以直接使用-32-bit parallel multiplier test paper has been verified, you can directly use
Platform: | Size: 1024 | Author: zh | Hits:

[Books] 32bits_float_muliplier

Description: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Platform: | Size: 97280 | Author: downloader | Hits:

[ADO-ODBC] 8bit_multi_pipeline

Description: 8 bit multiplier with pipeline design, mainly for studying and learning purpose
Platform: | Size: 1024 | Author: q | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[DSP program] MulPar

Description: 八位乘法器VHDL语言实现。使用的工具的ISE7.1，实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
Platform: | Size: 2048 | Author: 周东永 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

[Other] 8

Description: 移位相加8位硬件乘法器电路设计 乘法器是数字系统中的基本逻辑器件，在很多应用中都会出现如各种滤波器的设计、矩阵的运算等。本实验设计一个通用的8位乘法器。-Shift combined 8-bit hardware multiplier multiplier circuit design is a digital system in the basic logic devices, in many applications will emerge, and such a variety of filter design, such as matrix calculations. The experimental design of a generic 8-bit multiplier.
Platform: | Size: 5120 | Author: jun | Hits:

[VHDL-FPGA-Verilog] multiply

Description: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Platform: | Size: 1024 | Author: gulu | Hits:

[VHDL-FPGA-Verilog] multi8x8

Description: 实现了VHDL乘法器，8位乘法操作的完成-VHDL realize a multiplier, an 8-bit multiplication operation completed
Platform: | Size: 3072 | Author: zxzx | Hits:

[VHDL-FPGA-Verilog] 8-bit-Multiplier

Description: 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
Platform: | Size: 1024 | Author: 杨波 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplication through the principle of each shift to achieve, from the beginning of the lowest multiplicand, if 1, then left after the multiplier and the sum of the last if for 0, left after zero-sum in full, until the highest bit multiplicand.
Platform: | Size: 103424 | Author: lsp | Hits:

[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl)

Description: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Platform: | Size: 967680 | Author: jlz | Hits:

[VHDL-FPGA-Verilog] 8-by-8-Multiplier

Description: 8x8 bit multiplication verilog code
Platform: | Size: 50176 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] PARALLEL-MULTIPLIER

Description: vhdl code for a 32 bit parallel multiplier
Platform: | Size: 7168 | Author: sandeep kumar | Hits:
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